Question

Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 2, 4, 3, and 2 and P2 with a clock rate of 3.5 GHz and CPIs of 3, 3, 2, and 3.

a. Given a program with a dynamic instruction count of 1.0E8 instructions divided into classes as follows: 30% class A, 20% class B, 40% class C , and 10% class D which implementation is slower? P1 or P2?

b. What is the global CPI for each implementation?

c. Find the clock cycles required in both cases.

Answer 1

instu cHon CPICP) InsthucHon CJass IXio8 30.) C20%) (4o) Count 3 A 4 3 Cloc ate ()- 2.5 Gnz C ClouK ate 3.5 H2 2. 3 cPI CP esage o.2X4 + o.4x1+ 0*1X 2 O.32 2.8 cpI CPe 2-6 erecuton time (p) 20 O.11 2 Sec 25xI0 erecuton time (P= 8 O o743 Se c 3.5ID7 fore There 2.8 Gnlobal CPI CP) (P) 2.6 CPI Global reg wired in (p,) e o 2- 8 reg wired in 2 6xo8 gde U