Question

Exercise 3.24: Legal Assignments #1 Confirm that the statements below are legal (see main causes of mistakes in section 3.19) SIGNAL s1: BIT a) s2 (7) <=sl; SIGNAL s2: BIT_VECTOR ( 7 DowNTo 0); SIGNAL s3: STD LOGIC; b) s3 <s4 (0 ); c) s2 <= vl Xor "10001000 " ; SIGNAL s4: STD_LOGIC_VECTOR (7 DOWNTO o SIGNAL s5 INTEGER RANGE -35 TO 35; VARIABLE vl: BIT VECTOR(7 DOWNTO 0); d) s5 <v2/2; VARIABLE v2: INTEGER RANGE -35 TO 35;

Answer 1

All the below given statements are legal and the reasons are as follows :

a) s1 variable is bit type i.e. of 1 bit and it is assigned to the MSB of s2 variable that is legal, 1 bit assigned to 1 bit variable.

b) s3 is STD_LOGIC and size is not defined so by default it is 1 bit in size. Now s4 is a 8 bit sized vector whose MSB i.e. s4(0) is assigned to s3 that is also legal.

c) Here v1 is a 8 bit sized vector whose xor is done with a 8 bit sized vector and result is assigned to s2 that is also a 8 bit sized vector.

d) Here v2 is a integer type variable whose range is between -35 to 35. Now v2 is divided by 2 and result is saved in s5 which is also a variable of integer type ranging between -35 to 35. Now this is legal as whenever v2 is divided by 2, anyhow the result will be between -35 to 35 so it can be in the range of s5.