Question

b. Justify the reason for not recommending more than 4 pass transistors to be used in series for realizing logic circuits as shown in Figure 1. (9 Marks) M M ME 22 23 - -- Figure 1 exthren

Answer 1

Reference Book: VLSI Design By V.S.Bagad Ch:3 CMOS Logic Circuits

- ummm In such designs, logic signals are quite frequently required to pass through a number of pass transistors connected in series, consider chain of fous pass transistors connected in series, the gate of each of whom is connected to Ver Clogic!) as shown in your figure (given). Since all are connected to logic 1, the input signal propagates to the output. In order to investigate the delay involved in propergestion of the signal , we model this circit by the one shown in figure below. This network consists of those parameters associated with the pass transistors that contribute to delay 1 R v R V₂ o R , ve R V4 cŤ Tc" To I writing KCL at nocle V2 , ..cd ve I, I ₂ = (\, -V2)=(Y2_V3) dt - R Assume large number of pass transistors in series. Then equation reduces to RC dv = d'v

where R is resistance par unit length , is capacitance per unit length and x is distance along network from input. The propergention time taken by signal to propagate a distance a is directly proportioned to x². Let rand e be vaiables such that! R=rRs 1 Cico Cg are limped network elements R and C. Ther , R total = nr Rs total in cD Cg - ris the relative resistance per section interns of Rs and C is the relative capacitance per section interms of Dag. Then the total delay & for the n sections is given by {q = n2 cr(C) This as in increases the total deley rapidly increases and it is recommended that not more than four pass transistors be connected in segies.