Question

do a and b

CE228 Spring 2019 Qiz-2 Nane uestion-1: RAM [64 Pts.]: The followin mber of bits per word. rt (a): How many address lines and input-output data lines are needed in each case? g memories are specified by the number of words times the O. Number of Address LinesNumber of input/Output Lines 6 2 3 4 64M x 16 32G x 64 2M x 8 4256K x 16 8 ming the RA Ms in the table above use coincident decoding by splitting the internal decoder t(b d column decoders. What is the size of each internal decoder? Column Decoder Size Row Decoder Size Memory 64M x 16 32G x 32 2

Answer 1

a) 6 20 X 16 (AL) Addve slire= 26 (ilo lines) 16 5 30 DL) Data lines 35メ64 26 4、356 K x16 28 x 20x16 > 16 AL 26 26 = 2 x16 2 six of decode 26×2. . 32 x 32 2 Ru) (Colomn) 3S 21 2.