Some ISAs support the concept of an indirect jump. This is written as:
jr offset(rn) which does PC = Memory[rn + offset]
If this instruction was added to our pipelined MIPS, and assuming that one branch delay slot is used as is the current practice, how many extra stall cycles must be inserted for this instruction so that no unnecessary instructions are fetched? You must fully justify your answer.
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Some ISAs support the concept of an indirect jump. This is written as: jr offset(rn) which...