Question

Fig. 3 as follows is an IC layout of a CMOS implementation of a two-input digital logic gate. The truth table of the logic gate is also given. Voo Vini Vina Vout OVOV 3 V OV 3V 3 V Vint Vina out 3V10 V 3V 3V 3V OV GND Fig. 3 (a). How many MOSFETs are there in the IC layout shown above? (2 marks) (b). The given layout is drawn according to the lambda () design rules. If a = 0.15 um and the minimum feature size in the IC layout is 27, by examining the given layout or otherwise, determine the width in um of the MOSFET with the largest transistor size (i.e. W/L). (4 marks) (e). Using the given layout and your answer in (b), hence or otherwise, sketch the transistor schematic diagram of the two-input digital logic circuit. The MOSFETs must be labelled clearly with the transistor size corresponding to the layout (assuming = 0.15 um). (9 marks) (d). If the two inputs are tied together (i.e. Vini = Vin2), sketch the real DC voltage transfer characteristics (Vout Vs. Vin) of the CMOS digital logic circuit. Assume a supply voltage Vod = 3.0 V and the magnitude of the threshold voltage Vin] =0.5 V for the MOSFETs. All key features of the curve as well as the axes must be clearly labelled.

Answer 1

A)

From the truth table,it can be seen that the layout is of NAND gate

6

Vini Vina Vout OV OV 3V OV 3V 3V 3V10V OV 3V 3 V 3V 3V | 0V

Voo OLICI Vine Vina Vout BBB GND

The number of MOSFETS are 4 as rounded in the above figure

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B)

The width of NMOSes are 2*minimum feature size as shown below

Voo DI OLO Vina Vout BA GND

Given, minimum feature size is 2*lambda

Therefore, $w=2*2\lambda$

$w=2*2*0.15=0.6\mu m$

and

length l= minimum feature size

$l=2\lambda=2*0.15=0.3\mu m$

Therefore,

$(\frac{w}{l}){nmos}=2$

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C)