Question

In Lab

1. Check all the components for their working

2. Insert the appropriate IC into the IC base

3. Make connections as shown in the circuit diagram

4. Verify the Truth Table and observe the outputs

VCSQA QB QC QD CLK1 CLK2 14 13 12 11 10 9 00 IC 7495 1 2 3 4 5 6 7 B с MODE CONTROL GND SERIAL INPUT (Right PARALLEL Shift) INPUTS Lab Task 1: SERIAL IN SERIAL OUT (SISO) (Right Shift) Serial ip Shift Pulses QA Qв QC QD Data 0 1 0 t1 t2 t3 t4 t5 t6 t7 t8 X X X X

Answer 1

Taska - serial in parallel out (SIDO) Shift serial elp data Pulses O 0 o ti o O O ta O 1 1 t3 D After 1 O cú cik pulses tu el 1 Task 3: Parallel in parallel out (Pipo) clock input terminal shift pulses B o o O ti alka I no out (Piso) Taskun serial Parallel PO Q clock input Terminal QB shift Pulses o O ti A 0 Clka P o o I +2 Cika tz 1 o d O 1 tu I O 1 el X t5 X I 0 1

By knowing that all the components is working and proper Insertion of IC. into the IC base is taken place and also all connections are correct like PD the ckt diagram QC QD Clki cik2 VCC lu 13 12 il 13 a & IC7495 2 3 4 5 6 그 C D GND Serial Tlp (Rs) Parallel alp's Task 12 serial serial out (SISO) (Right Shift) QC Iserial Elp Data shift pulses intial O - O ti o 1 t2 I 0 o 1 o t3 I 0 ty 1 O 1 O 1 I ts x x I 0 Х to X X ta X I x X X x X X to X x X - means either o or's