Question

Given the following circuit with the variable inputs, derive the Boolean expression, simplify the expression using a Karnaugh map and Write the VHDL code. [10] F THE END

Answer 1

Given a. circuit with inputs X, Y, Z and output F from the figure = ū+z) (ý + ž tă+y)(x+y+z) + = (2+z) + ( a +3+1) + (a+y + (using Demorgan's Law Ātbt $+$ 21) . ABC 2. 1+A3 A1 z (á 7) + + (x+y+z) (T=o) By Using demorgan's law A+B= A Xătatyt (2+1)7 + + hay x+y+z (1 +A= 1) F (x+y+z) By Karnaugh map 1 2 ५२ 00 Ol lo 1 - F = (a+y+7) -

library iece, use ieee std-logic- 1164 all; use ieee.std-logic-arith-alle entity module is port (x,y,z in std logic; F ; out std logic); end module Architecture datatlow of modul is begin x ory of (~Z); end dataflow;