Question

X 54-bit Input Buffers X54bit 27 bit A Dir 27 bit Y 54-bit input Buffers Booth Encoders Add. 27 bit PPGs To Partial Product Generator) & Compressors (28-2, 27-2, 26-2, ..., 9-2, 4-2, FA, and HA) 108 bit 108 bit 108-bit XCSA Adder 108 bit 108-bit Final Sum

Answer 1

Booth encodex multiplication implementation and partial Product generatoon is in Ao register paise as shown below: Multiplicand (MD) Two complements Generator Multiplice Booth posuz Partial Product Generatore PP.7 Plo V LV V V look - Ahead Carry look - A Adder u-Bit Multiplication: (-7) (-3) soo1 1101 Bit Pairs Multiplier Paire with G I o ta wana + IT T 1 2 0 1 : Recoded Multiplier ist of tt-1

Multiplicant M: 1001 & County А 0 9.4 0000 11 01 0 : initial ol1 oo11 JO1 LITO – 0 : AEA-M 1 : ASR Count=3 oooo Jool OS 11 1100 1130 ITIO OSII 1 AGAIM 0: ASR count=2 oo 11 Joon 7100 O IST Jolt oo 10 0 : ACA-M to ASR Count=f 1110 1001 OJOJ ooof os of To ASR count=0

(start) Me multiplicand QE Multiplier 9-s, AEO Counten . 10 0 GA 00 OT ACA-M LAE ATM ASR AQ, 9-1 1 Count & Count -1 ] [ASR= Authmatic shift right] Final Product is in Al register pair es Stop Count