Question

Exercises: 1. Write the VHDL statements to describe a 4-bit comparator. Use the appropriate relational operators. Use input ports A and B, described above, as the inputs to the 4-bit comparator. Assume that three output ports, EQ, GT, and LT, have been declared in the Entity statement. Use them as the outputs from the comparator 2. Identify the package (or packages) that must be included in your VHDL code in order to use the relational operators with signals of type STD LOGIC or STD_LOGIC.VECTOR. Remember that you are designing an unsigned comparator. Provide your answer below

Answer 1