Consider the delays from Table 7.5. Now suppose that the ALU were 20% faster. Would the cycle time of the pipelined ARM processor change? What if the ALU were 20% slower?
Consider the delays from Table 7.5. Now suppose that the ALU were 20% faster. Would the...
6. Consider a datapath similar to the one in figure below, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would the cycle time be for this datapath? PCSrc Add ALU Add result Shift +( left 2 Read register 1 ALUSrc, 4 ALU operation PCRead PC-address Read data 1 Registers Read data 2 MemWrite Zero ALU ALU-I Address MemtoReg Instruction register 2 Instruction | Write Read data-M register Write Lu memory Write Data data...