Q3) Design a CMOs ckt with the function A.(BC+DE) The less transistors, the more points.
Design AND and OR gates using CMOS transistors, Can use 2 transistors per input and out must either pull to ground or to Voltage source.
1. a. Design and implement a 2 bit comparator circuit using CMOS transistors(Greater than,less than, equal to or reverse). b. Draw the mask layout with Ln = Lp= 0.6 μm, Wn= 4.8 μm and Wp= 7.8 μm using 0.6 μm technology. Also simulate the design using microwind tool and verify the outputs.
electronics II 35 points 1. Design the CMOS logic Y = A·(B+C) using 4 n-channel transistors and 4 p-channel transistors, where A, B, and C are the three different input signals and Y is the output.
Design and implement a 4 bit- binary to gray code converter using CMOS transistors. (30 Marks) (Note: Students are expected to design the circuit with truth table, solve the output expression (by use of K Map or suitable circuit Reduction technique) and implement using CMOS transistors.)
1. a. Design and implement a 2 bit comparator circuit using CMOS transistors(Greater than,less than, equal to or reverse). b. Draw the mask layout with Ln = Lp= 0.6 μm, Wn= 4.8 μm and Wp= 7.8 μm using 0.6 μm technology. Also simulate the design using microwind tool and verify the outputs.
7.83. Design a CMOS logic gate that implements the logic function Y-ABC+ DE) and is twice as fast as the CMOS reference inverter when loaded by a capacitance of 2C
1. Design and implement a full subtractor circuit using CMOS transistors. (30 Marks) (Note: Students are expected to design the circuit with truth table, solve the output expression (by use of K Map or suitable circuit Reduction technique) and implement using CMOS transistors.) p.s: simplify the k map equation (with minimum expressions) then draw the cmos transistors.
1. Design and implement a 4 to 1 multiplexer circuit using CMOS transistors. (30 Marks) (Note: Students are expected to design the circuit with truth table, solve the output expression by use of K Map or suitable circuit Reduction technique and implement using CMOS transistors.)
3. Design the CMOS gate that implements the following function OUT- AB (a) Draw the circuit schematic without any output inverter. (b) Size all the transistors in this circuit such that TR 3Tr. The minimum geometry is W. 3. Design the CMOS gate that implements the following function OUT- AB (a) Draw the circuit schematic without any output inverter. (b) Size all the transistors in this circuit such that TR 3Tr. The minimum geometry is W.
(Pull-Up/Pull-Down Network in CMOS gates - 20 points) Consider the pull-down network (consisting of NMOS transistors) of a CMOS gate as shown in Fig. 1. Construct the corresponding pull-up network consisting of PMOS transistors. Recall, the pull-up and pull-down networks are duals of each other. Also derive the logic function implemented by the gate. Briefly state the reasoning behind your design. What would this Pull-ujp network look like?