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3. Construct a modulo-5 parallel (synchronous) down counter using master-slave T flip- flops. The counter should...
Design serial (asynchronous) counter modulo 7 using synchronous flip-flops (T, D or JK). The counter should count up.
SP-5. Design a modulo-8 Gray code counter using D-type Master-Slave flip-flops. Show the logic diagram. (Use CMOS transistor networks for the combinational circuits.)
(b)(i) Using T flip-flop as main components, design a 3-bit synchronous counter that perform counting as the following sequence 0,2,4,6,1,3,5,7 then repeats (its sequence) [20 marks] (ii) Draw a complete circuit to show how the T flip-flops are interconnected and label it appropriately. Also show how the counter can be asynchronous reset. [5 marks] (iii) Draw a timing diagram for at least four clock cycles [8 marks)
Design a counter to count-up from 2 to 5 using 3 D Flip-Flops similar to the following sample: Important Steps: After you simplify D2, D1 and DO by kmap Have a piece of paper to draw it then open iCircuit to design it using BCD If it works well as a counter, copy the design from iCircuit and paste it here. 3-Bit Counter Using D Flip-Flop: The State Equation of D Flip-Flop: Q(t+1)=D(t) => Dn=An Count Up From 3 To...