Question

unsure how to proceed, any help would be greatly appreciated!

4. Create the logic circuit for a 12-bit PWM that creates a duty cycle of approximately 70%. Use as many 4-bit synchronous counters and 4-bit comparators as needed. Schematic of each is shown below. A3 8888 OAGTB OAKOB OALTB AZ B2 AI ENT TIIT TILL АО - -LOAD BO -CLR - CLK AGTB AEOR ALTB CNTR_4BIN S COMP_4

Answer 1

Some inputs to help you design this circuit:

1. As we need to build a 12-bit PWM, therefore we need to cascade 3 counters here

2. The final count in 12 bits is 4095 (FFF Hex). Its 70% is 2866.5. We round it off to 2867 (B33 Hex).

3. Therefore we need an output that remains high while the count of cascaded counters is less than B33 Hex. It should go to zero when count is from B34 Hex to FFF Hex.

4. To accomplish step 3 above, we need a 12-bit counter.

5. This counter can be made by cascading three 4-bit counters.

6. Next we need three comparators. The comparators shown in the problem statement have three outputs, namely AGTB (i.e. A>B) , AEQB (i.e A==B) and ALTB (i.e A<B)

7. Of these we can use AGTB and ALTB

8. The 12 B inputs of the three cascaded comparator are fixed at B33 Hex

9. The 12 A inputs of cascaded comparators receive their input from the cascaded counters.

10. The first layer of comparators compares the three nibbles coming in from the counters against B33 Hex

11. The fourth comparator compares the output of three comparators and generates the final PWM output

12. Please see the diagram below where I have tried to explain this idea. You will have to excuse me for rough drawing though.

13. Please note that this design does not show every detail (such as IC power supply, unused counter inputs etc)

14. For cascading of synchronous counters please see http://www2.elo.utfsm.cl/~lsb/elo211/aplicaciones/katz/chapter7/chapter07.doc5.html

15. For cascading of comparators you could refer to: http://www.ti.com/lit/ds/symlink/sn74ls85.pdf

PWM Сот от LAB NB PEAB ALTB # HALB L ÃO A A2 A3 B4 61 B2 B3] Xolxlx 11 YOY Y PGTB AEAB ALTB AGT AES ALB yo X27 77% AGTB AEQB ALTB LAZB SAB ALBA A A2 A Be Bi Bi Bul A43 HALB parroc III (3) JENT Q Q Q a pot -OLLA holcic da = LSB

A quick verification at two inputs values at the final counter (one less than B33 hex and the other more than B33 Hex)

Counter output X2 X1 X0 Y2 Y1 Y0    PWM Output

800 Hex    0    0    0 1    1 1 1

C00 Hex 1 0 0 0 1 1 0

(At the final comparator X2 X1 X0 are compared against Y2 Y1 Y0)

Hope this helps.