Question

8) Answer the following questions for the 4-function ALU described below: Si So Function 00 Pass A 0 1 A ORB 110 A B 11 A-1 a) What would the Boolean equations for the LE, AE, and CE be? b) Draw the circuit for only the lowest order bit, A, and Bo- c) Write the Behavioral VHDL code for an 8-bit version of the ALU described above.

Answer 1

Design an ALU that can perform four operations: Pass A, OR ,addition and subtraction. we will need two select lines, s1 and s0 , because two bits will give four different combinations (00, 01, 10 and 11).Therefore the outputs of the LE, AE and CE are dependent on which operation we want to perform, therefore, the select lines are also inputs to LE, AE and CE circuits.

So for the combination s1 s0 = 00, we will perform the pass A operation. we just pass A value, thus, the LE will output Ai (the i th bit of A) and the AE will output a 0.also CE will output a 0.

for the combination s1 s0 = 01 where the ALU will perform the logical OR operation, the LE will output the result of Ai OR Bi . For all logical operations, we do not want the FAs to add anything, so the AE, which outputs to the second operand of the FA, should output a 0. Similarly, the CE should output a 0.

So for the combination s1 s0 = 10,it will perform the addition of A + B. And just like adder/subtractor circuit, we want the first operand to the Fulladder to be A and the second operand to the Fulladder to be B, thus, the LE will output Ai (the i th bit of A) and the AE will output Bi (the i th bit of B).in adder/ subtractor circuit for addition, we need the initial carry-in c0 to be a 0,There fore CE will output a 0.

For the combination s1 s0 = 11,it will perform the subtraction of A – B. In the adder/subtractor circuit for subtraction, we need to invert the second operand B of Fulladder and then add a 1 through the initial carry-in c0 . Therefore the AE will output Bi ’ and the CE will output a 1.

The following table shows output value for LE,AE and CE circuits

s1	s0	Function	xi (LE)	yi (AE)	c0 (CE)
0	0	Pass A	Ai	0	0
0	1	A or B	Ai OR Bi	0	0
1	0	A+B	Ai	Bi	0
1	1	A-B	Ai	Bi ’	1

ALU extender circuits: logic extender (LE); arithmetic extender (AE); carry extender (CE)

1. What would be the Boolean equations for LE,AE and CE be?

Answer:

Followings are Boolean equations for LE,AE and CE circuits

LE=S1’S0’A0+A0+S0S1’B0

AE=S1’+S0’B0+S0B0’

CE=S1S0

2. Draw the circuit for only lowest order bit,A0 & B0

Answer:
Ao Bo So CE (C) AEC) LE () (mi Cany.m Fulladder S0 Sipes eveese

3. Behavioural VHDL code for 8 bit ALU

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity alu is

Port ( inp_a : in signed(7 downto 0);

inp_b : in signed(7 downto 0);

sel : in STD_LOGIC_VECTOR (1 downto 0);

out_alu : out signed(7 downto 0); cout : out std_logic);

end alu;

architecture Behavioral of alu is

begin

process(inp_a, inp_b, sel)

signal LE,AE,CE:signed;

begin

case sel is

when "00" =>

LE<=((not sel(1) ) and (not sel(0)) and (inp_a) ) or (inp_a) or ((not sel(1) ) and (sel(0)) and (inp_b) )

AE<=(not sel(1) ) or ((not sel(0)) and (inp_b) ) or ( sel(0) and (not(inp_b) ) )

CE<= sel(1) and sel(0)

out_alu<= LE xor AE xor CE; --pass A

cout<= LE and AE or AE and CE or CE and LE;

when "01" =>

LE<=((not sel(1) ) and (not sel(0)) and (inp_a) ) or (inp_a) or ((not sel(1) ) and (sel(0)) and (inp_b) )

AE<=(not sel(1) ) or ((not sel(0)) and (inp_b) ) or ( sel(0) and (not(inp_b) ) )

CE<= sel(1) and sel(0)

out_alu<= LE xor AE xor CE; --OR gate

cout<= LE and AE or AE and CE or CE and LE;

when "10" =>

LE<=((not sel(1) ) and (not sel(0)) and (inp_a) ) or (inp_a) or ((not sel(1) ) and (sel(0)) and (inp_b) )

AE<=(not sel(1) ) or ((not sel(0)) and (inp_b) ) or ( sel(0) and (not(inp_b) ) )

CE<= sel(1) and sel(0)

out_alu<= LE xor AE xor CE; --addition

cout<= LE and AE or AE and CE or CE and LE;

when "11" =>

LE<=((not sel(1) ) and (not sel(0)) and (inp_a) ) or (inp_a) or ((not sel(1) ) and (sel(0)) and (inp_b) )

AE<=(not sel(1) ) or ((not sel(0)) and (inp_b) ) or ( sel(0) and (not(inp_b) ) )

CE<= sel(1) and sel(0)

out_alu<= LE xor AE xor CE; --subtraction

cout<= LE and AE or AE and CE or CE and LE;

when others =>

NULL;

end case;

end process;

end Behavioral;

--------------------------------------- OR----------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity alu is
Port ( inp_a : in signed(7 downto 0);
inp_b : in signed(7 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
out_alu : out signed(7 downto 0));
end alu;

architecture Behavioral of alu is
begin
process(inp_a, inp_b, sel)
begin
case sel is
when "00" =>
out_alu<= inp_a; --pass A
when "01" =>
out_alu<= inp_a or inp_b; --OR gate
when "10" =>
out_alu<= inp_a + inp_b; --addition
when "11" =>
out_alu<= inp_a - inp_b; --subtraction
when others =>
NULL;
end case;
  
end process;

end Behavioral;