Question

Q5) A combinational circuit with internal signals and signal propagation delays Shown below is a combination circuit that takes 5 inputs (LO L1, L2, L3, and Comp), and generates 4 outputs (L4, L5, L6, し7) Please design the entity as well as the test bench for this combinational circuit. In your design, please set up internal signals Al, B, A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7 and B7 Your entity design is Your test bench design is: In your test bench design, please let L0, Li, L2, L3 to go through "0000" "0001 "0010", "0011", "0100", "0101" "O110". "40111".-000". 4.1001". .. 1010"、 "1011 .. 1100'. 1101", "1", each at a period of 100ns. Do this for COMP = '0' first, and then let COMP-1 .

Answer 1

Verilog code for entity design

module satHomeworkLib(comp,L0,L1,L2,L3,L5,L6,L7,L4);
input comp,L0,L1,L2,L3;
output L4,L5,L6,L7;
wire A1,A2,A3,A4,A5,A6,A7,B1,B2,B3,B4,B5,B6,B7;
assign A1=L0;
assign A2=L1;
assign A3=L1;
assign A4=L2;
assign A5=L2;
assign A6=L3;
assign A7=L3;
assign B6=comp;
assign B7=comp;
assign B5=A6|B6;
assign B4=B5;
assign B3=A4|B4;
assign B2=B3;
assign B1=A2|B2;
assign L4=A1^B1;
assign L5=A3^B3;
assign L6=A5^B5;
assign L7=A7^B7;
endmodule

Test bench for comp=0

module test;
reg comp,L0,L1,L2,L3;
wire L4,L5,L6,L7;
satHomeworkLib uut(comp,L0,L1,L2,L3,L5,L6,L7,L4);
initial
begin
comp=0;L0=0;L1=0;L2=0;L3=0;
#100 L0=0;L1=0;L2=0;L3=1;
#100 L0=0;L1=0;L2=1;L3=0;
#100 L0=0;L1=0;L2=1;L3=1;
#100 L0=0;L1=1;L2=0;L3=0;
#100 L0=0;L1=1;L2=0;L3=1;
#100 L0=0;L1=1;L2=1;L3=0;
#100 L0=0;L1=1;L2=1;L3=1;
#100 L0=1;L1=0;L2=0;L3=0;
#100 L0=1;L1=0;L2=0;L3=1;
#100 L0=1;L1=0;L2=1;L3=0;
#100 L0=1;L1=0;L2=1;L3=1;
#100 L0=1;L1=1;L2=0;L3=0;
#100 L0=1;L1=1;L2=0;L3=1;
#100 L0=1;L1=1;L2=1;L3=0;
#100 L0=1;L1=1;L2=1;L3=1;
end
endmodule

Testbench for comp=1

module test1;
reg comp,L0,L1,L2,L3;
wire L4,L5,L6,L7;
satHomeworkLib uut(comp,L0,L1,L2,L3,L5,L6,L7,L4);
initial
begin
#100 comp=1;L0=0;L1=0;L2=0;L3=0;
#100 L0=0;L1=0;L2=0;L3=1;
#100 L0=0;L1=0;L2=1;L3=0;
#100 L0=0;L1=0;L2=1;L3=1;
#100 L0=0;L1=1;L2=0;L3=0;
#100 L0=0;L1=1;L2=0;L3=1;
#100 L0=0;L1=1;L2=1;L3=0;
#100 L0=0;L1=1;L2=1;L3=1;
#100 L0=1;L1=0;L2=0;L3=0;
#100 L0=1;L1=0;L2=0;L3=1;
#100 L0=1;L1=0;L2=1;L3=0;
#100 L0=1;L1=0;L2=1;L3=1;
#100 L0=1;L1=1;L2=0;L3=0;
#100 L0=1;L1=1;L2=0;L3=1;
#100 L0=1;L1=1;L2=1;L3=0;
#100 L0=1;L1=1;L2=1;L3=1;
end
endmodule

Waveforms for comp=0

Waveforms for comp=1

600 n 700 2E 00 ns 400 500 n Value 200 ns 100 ns

Entity design when considering delays

Untted 3 00 ne 00 ns 500 ne Value 100 ns 200 n 300 n comp

module satHomeworkLib(comp,L0,L1,L2,L3,L5,L6,L7,L4);
input comp,L0,L1,L2,L3;
output L4,L5,L6,L7;
wire A1,A2,A3,A4,A5,A6,A7,B1,B2,B3,B4,B5,B6,B7;
assign A1=L0;
assign A2=L1;
assign A3=L1;
assign A4=L2;
assign A5=L2;
assign A6=L3;
assign A7=L3;
assign B6=comp;
assign B7=comp;
assign#4 B5=A6|B6;
assign B4=B5;
assign#4 B3=A4|B4;
assign B2=B3;
assign#4 B1=A2|B2;
assign#10 L4=A1^B1;
assign#10 L5=A3^B3;
assign#10 L6=A5^B5;
assign#10 L7=A7^B7;
endmodule

You can use above test bench codes.

Waveforms for comp=0

Waveforms for comp=1

Untited 4 Valuc On費 00 ne 200 n s00 ns comp Open Implemented Design Type a Tel conmand hete Program and Debug 里Td Console Messages l园Log」