Question

stem Decode esign a memory system with the following attributes: 64k × 16 total address space ROM modules are each 16k x 16 modules RAM modules are 16K x 8 (hint: you need two (2) RAM modules correctly enabled together for 16-bit output) Device Modules are 4K x 16 Use 2x4 decoders and show all address, data and control signals to match the memory map of the system below ROM RAM Device1 Device2 0x0000-0x7FFF 0x8000-OxBFFF Device3 Device4 0xD000-0xDFFF OxE000-OxEFFF OxF000-OxFFFF

Answer 1

Block Diagram

Note: RD - Read , WR - Write, CS- Chip Select

x - don't care, either 0 or 1

Explanation:

Size of address and data bus for CPU : Total address space is 64K x 16 = (2⁶ x 2¹⁰) x 16 = 2¹⁶ x 16 [ K=2¹⁰]

The size of address bus = 16

The size of data bus = 16

For ROM : Size of ROM is 16K x 16 =( 2⁴ x 2¹⁰) x 16 = 2¹⁴ x 16

The size of address bus = 14

The size of data bus = 16

For RAM: Size of one RAM module is 16K x 8 = ( 2⁴ x 2¹⁰) x 8 = 2¹⁴ x 8

We have to use 2 RAM module to get RAM size of 16K x 16. The two RAM modules will be accessed simultaneously by the same address generated by the CPU.

The size of the address bus will remain fixed to 14.

The size of the data bus will be 8 + 8 = 16, as shown in the above figure.

For each Device: The size of device module is 4K x 16 = (2² x 2¹⁰) x 16 = 2¹² x 16

The size of address bus = 12

The size of data bus = 16  

Selection of components:

Above components are selected when CS1=1 and CS2=0.

Address lines 16-13 are used to select above components and the selection table is given below:

	Address lines
Components	16	15	14	13
ROM	0	x	x	x
RAM	1	0	x	x
Device1	1	1	0	0
Device2	1	1	0	1
Device3	1	1	1	0
Device4	1	1	1	1

ROM : It's selected when address line 16 is zero, i.e CS2=0. CS1 of ROM is connected with RD line because only read operation is possible in ROM.

In other words ROM is selected when address line 16 is zero and RD signal is high(1).

RAM: It's selected when address line 16 is one and address line 15 is zero since address line 16 is connected to CS1 and address line 15 is connected to CS2.

Given the size of RAM is 16K x 8. Inorder to get a RAM module of size 16K x 16, we require 2 RAM module of size 16K x 8. As shown in the figure above there are two RAM each of size 16K x 8. The data lines of these two RAM are combine together to form a data lines of size 16.

Devices: A device is selected when both address lines 16 and 15 are one. Address line 16 and 15 are the two inputs of the AND gate which output is connected to the Enable(E) input of a 2 x 4 decoder. It means 2 x 4 decoder is enabled when both address lines 16 and 15 are one.

CS1 of all the output devices are connected with WR line, because only write operation is possible in the output device.

Address line 14 and 13 goes to a 2 x 4 decoder which is used to select any one device out of the 4 devices with WR line must be high(1).