Problem 4 (28 points). a) (20 points) Using row and column addressing, design a 64 Mb...
3. Virtual Memory (20 points) An ISA supports an 8 bit, byte-addressable virtual address space. The corresponding physical memory has only 256 bytes. Each page contains 32 bytes. A simple, one-level translation scheme is used and the page table resides in physical memory. The initial contents of the frames of physical memory are shown below. VALUE address size 8 bit byte addressable each byte of addressing type memory has its own address 32 B page size physical memory size 256...
Problem #1 (25 points) Address Space, Memory Consider a hypothetical 18-bit processor called HYP18 with all registers, including PC and SP, being 18 bits long. The smallest addressable unit in memory is an 8-bit byte. A. (4 points) What is the size of HYP18's address space in bytes and KB? How many address lines does HYP18 require? Address space: Bytes Address space: KB (KiloBytes). Address bus lines: B. (6 points) Assume that first quarter of the address space is dedicated...
Assume the cache can hold 64 kB. Data are transferred between main memory and the cache in blocks of 4 bytes each. This means that the cache is organized as 16K=2^14 lines of 4 bytes each. The main memory consists of 16 MB, with each byte directly addressable by a 24-bit address (2^24 =16M). Thus, for mapping purposes, we can consider main memory to consist of 4M blocks of 4 bytes each. Please show illustrations too for all work. Part...