23. The number of quantization levels of a 5 bit Analog to Digital converter is _____
a. 64 levels |
b. 128 levels |
c. 16 levels |
d. 32 levels |
24. If a timer is running a PWM output signal with period T=1 ms then for a 50% duty cycle, Ton is? |
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25. An 8-bit timer/counter can have a maximum value of ________ |
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23. The number of quantization levels of a 5 bit Analog to Digital converter is...
How many gray levels will an 8-bit ADC (analog-to-digital converter) produce? A) 8 B) 64 C) 256 D) 1024
When designing an Analog to Digital System all of the range values for the system must be defined from input to output. This input will be used to drive a 3. PWM output signal to operate an LED. Assume the PWM is calibrated to read minimum to maximum based on the binary input range given. Potentiometer - 10 KS2 (0 degrees to 180 degrees) VDC for Potentiometer 12 V Analog Converter Module 10 bit, Vref 8 V PWM Module-8 bit,...
Q1) Digital-to-Analog Conversion The signal shown in the figure below is inserted to a 5-bit ADC converter Considering, the useful range of the converter is 0-3V, draw the values obtained in the ADC output register when the sampling time is a) 1ms, and b) 0.5ms 3 1.5 16 [ms] 8 0 12 a) 4t ms Reg. value 16 ms] 12 4 0 b) 4t 0.5ms Reg. value 16 t [ms] 12 4 8 Q1) Digital-to-Analog Conversion The signal shown in...
Multiple Choice 11. The ________ is the agreed-upon interface between all the software that runs on the machine and the hardware that executes it. It allows you to talk to the machine. A) hardware protocol B) software protocol C) machine control architecture D) instruction set architecture 12. A ________ consists of an arithmetic logic unit and a control unit. A) processor B) computer C) register D) program 13. ________ are typically used by companies for specific applications such as data...