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Strained-Si (10%) nd nMOS made on Hitachis SiGe Virtual Substrate, published at IED 2001, demonstrated excellent performance of both What are the major physical reason to prevent this tec (b) What are the methods to apply strain into Intels p- and higher electron and hole mobility hnology into real manufacture n-MOS?

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Answer #1

A)The Band OFFSET in SiGe is used to increase mobility.

1)for p - MOS most holes in the channel are confined to SiGe

2)for n-MOSFET a fraction of channel electrons move in SiGe

Band offset and strain properties improve performanceEc Ev 18A 40A 100A 18A 40A 100A p-MOSFET n-MOSFET

introducing Ge in Si-mos improves performance

an additional increase in mobility is induced by strain

B) NMOS strain was introduced by adding a high-stress layer that wrapped around the transistor (a process sometimes named CESL, or contact etch-stop layer after the most common layer used for the stressor). PMOS strain was introduced by replacing the conventional source/drain region with strained SiGe (a process often called embedded-SiGe or e-SiGe). The addition of strain in both NMOS and PMOS enhanced the channel mobility, resulting in improved drive current (and improved performance) for both NMOS and PMOS.

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