Question

Now, you are asked to implement 5 I/O devices (same as the devices in the previous question) that are addressed to the ports given (hex values) in the table: Device # 8A9 8B9 8AB 8AD 8AF AA9 AB9 AAB AAD AAF Ports used CA9 CB9 CAB CAD CAF EA9 EB9 EAB EAD EAF 4 Write the binary representation of the ports on each device, using don't cares (x) for the individual port select bits (or hex nibbles) on the device. I started it for you. a. Device # x A9 x B9 1 x x 0 1010 1001 X AF 1 x x0 1010 1111 b. Based on your work (above), what address bits would go to the decoder select lines? Based on your work in (a) and (b), what bits form the enable lines for the entire I/O device structure? c. d. Draw the decoding logic for this implementation, properly showing all chip selects, address lines, and enable lines. Use the 74LS138 decoder (given) along with AND, OR, and NOT gates as required ?2 15DYO

Answer 1

Answer a:

Device		Port Hex	Port Binary 1xx0 (1,A0,A1,A2) (1,E1,E2,E3)
0		X A9	1xx0 1010 1001
1		X B9	1xx0 1011 1001
2		X AB	1xx0 1010 1011
3		X AD	1xx0 1010 1101
4		X AF	1xx0 1010 1111

Answer b:Address lines will be A0,A1,A2 for the entire input output structure see the answer a for reference in column port Binary column.

Answer c:Enable lines will be E0,E1,E2 for the entire input output structure see the answer a for reference in column port Binary column.

Answer d: main logic diagram:

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