Question

In a dual-voltage CMOS integrated circuit, output driver high-voltage and internal low-voltage transistors operate at supply voltages of 2.5V and 0.8V, respectively. To fabricate the devices, 150 nm technology node with tox = 5 nm is used, along with threshold voltages of VTN = |VTP| = 0.25V. Both high-voltage and low-voltage circuits must be able to drive 5 pF off-chip loads with a maximum propagation delay of 250 ps. Please determine the minimum widths of both highvoltage (output driver) and low-voltage (internal circuit) transistors accordingly

Answer 1

Solution In election In Silicon, & M: 1500 x 10-4 m/ 475 410 4 m/vs Con 2 Cr Con 11.9x8.85x10-12 . 0.02 f/m2 5810-9 50 Mylen: 3.16 mA) ² Veld coir Alplex . IMA/V2. Sizing 0.8v denne. for NMDS tp. Ron C m2. = 250ps & Ron 250x10-2 5810-12 x mg 2) Ron: 722. Rona 3.96420") ( Mos en Won (Vas-Ven) (0-8-0.25) ( 3.16 *103 x 0-55X72

fost pmos (9) Celular con -> () ** (07-015) > (W): 1475 so has low voltage denne (2670-80) (W): 8, (), 2525 fas high voltage dence 8x (0.8-0.25) Do 73.5-0.25) 196 1.9673 16- 6-18 so for high vollage dence (Voor 25v) ( 2 ) = 1.96 (W) p = 6-18