Question

Assume the clock frequency is 9 MHz, calculate the total delay when the instruction CALL DELAY_ME is executed.

^{[17, 20, 25, 33, 35]}

DELAY_ME: LDI R21,25 ; 1 clock cycle

LOOP_D2: RCALL DELAY0 ;

RCALL DELAY0 ;

RCALL DELAY0 ;

NOP ; 1 clock cycle

DEC R21 ; 1 clock cycle

BRNE LOOP_D2 ; 1/2 clock cycle(s)

LDI R17,5 ; 1 clock cycle

EXTRA_D2: DEC R17 ; 1 clock cycle

BRNE EXTRA_D2 ; 1/2 clock cycle(s)

NOP ; 1 clock cycle

NOP ; 1 clock cycle

RET

DELAY0: LDI R20,73 ; 1 clock cycle

OUTER_D1: LDI R16,72 ; 1 clock cycle

INNER_D1: DEC R16 ; 1 clock cycle

BRNE INNER_D1 ; 1 or 2 clock cycles

DEC R20 ; 1 clock cycle

BRNE OUTER_D1 ; 1 or 2 clock cycles

NOP ; 1 clock cycle

NOP ; 1 clock cycle

NOP ; 1 clock cycle

RET ; 4 clock cycles

The total delay in milliseconds is

Answer 1

The clock frequency of the board is 9 MHz. Hence, the duration of a single clock cycle is 1/(9*10^6) = 0.11 uses; where u stands for microseconds. Now, inside the DELAY-ME subroutine, 3 times DELAYO loop has been called. Hence, the total clock cycles of the DELAYO subroutine are (INNER_D1 and OUTER_D1 subroutines are executed for 72 and 73 times respectively). 3*(1+1+(1+1)*72+2+(1+1)*73+2+4*1) = 900 clock cycle. Therefore, the total clock cycle of the DELAY-ME subroutine is (LOOP_D2 calls 24 times, and EXTRA_D2 calls 5 times) 1+(900+1+1)*24+2+1+(1+1)*5+2+2*1 = 21666 clock cycle. Thus the total delay is Total clock cycle * time of single clock cycle = 21666*0.11 uses = 2.38 msec.