Mark all of the following that are valid design reasons that the FP and integer registers in the MIPS ISA are logically separated
A. The original MIPS ISA used a co-processor model for communicating with the floating-point unit
B. Integer instructions rarely use floating point operands, and vice versa
C. Integer operands are big endian and floating point operands are little endian
D. Floating point registers need their bits stored on floating gates
From the question:
Valid design reasons that the FP and integer registers in the MIPS ISA are logically separated
Option A and B are correct
Mark all of the following that are valid design reasons that the FP and integer registers...
Mark all of the following that are valid design reasons that the FP and integer registers in the MIPS DLX ISA are logically separated Floating point registers need their bits stored on floating gates Integer operands are big endian and floating point operands are little endiarn The original MIPS ISA used a co-processor model for communicating with the floating-point unit Integer instructions rarely use floating point operands, and vice versa
Some processors have two sets of registers, one for integer operations and one for floating point (fp) operations. The registers used in integer operations are always saved and restored during every context switch whether it is preemptive multithreading or non-preemptive multithreading(since they are also used for calculations for instructions, such as memory address calculation, branch target calculation etc.) However, for most machines it is not very clear what will happen to the floating-point registers. Below you are given 5 different...