36.-Assume a 32 bit memory space with 16[KB] pages/frames and a two-level page table. Answer the following questions: a).-what is the size of the page table in bytes needed for a process that has only 64[MB] of code at the start of its virtual address range? b).-how many bits are used for address (frame) offset, and how many for page table indexing (total). Assume each page table entry has 32 bits.
a).-Size of page table |
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b).-Offset bits |
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b).-Page table indexing bits |
Even though the process occupies 64MB of space it will be expressed as 32bit addresses..
Here since nothing was mentioned I have assumed that 1st level page table is divided into equal size pages of page size 16KB.
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36.-Assume a 32 bit memory space with 16[KB] pages/frames and a two-level page table. Answer the...
Exercise l: Suppose that we have a virtual memory space of 28 bytes for a given process and physical memory of 4 page frames. There is no cache. Suppose that pages are 32 bytes in length. 1) How many bits the virtual address contain? How many bits the physical address contain? bs Suppose now that some pages from the process have been brought into main memory as shown in the following figure: Virtual memory Physical memory Page table Frame #...
Consider a virtual memory system with the following properties: 36 bit virtual byte address, 8 KB pages size, and 32 bit physical byte address. Please explain how you determined your answer. a. What is the size of main memory for this system if all addressable frames are used? b. What is the total size of the page table for each process on this processor, assuming that the valid, protection, dirty, and use bits take a total of 4 bits and...
computer architecture
Virtual memory 4 physice memar Assume a 64 bit machine with 40 bit addresses, and 16GB of actual memory. Memory blocks are 4K 1. How many bits in the virtual memory INDEX and OFFSET fields? 2. What fields do you need in a page table entry, and how many bits are needed for each? How many bytes do you need for each page table entry? (each entry is allocated in a whole number of bytes, even if there...
4. Assume that we have a machine with the following memory specifications: Virtual addresses are 32 bits wide Physical addresses are 26 bits wide . Page size is 16 Kbytes 4/A) How many pages are in the virtual memory space? 4/B) How many page frames are in the physical memory space? 4/C) If each page table entry consists of a physical frame number, 1 present/absent bit Answers Pages .Page Frames and 1 dirty/clean bit (which shows if the page has...
Main memory has 1,024 bytes, and frames are 32
bits. Assume a portion of main memory, and the page table,
shown below. The frame numbers in the Page Table are shown as base
10, but all other data in the tables is either binary or hex. A TLB
is not used. The virtual address space for each process is 8 pages.
The first frame in memory is frame 0, but only a portion of memory
is shown (not necessarily that...
Consider a logical address space of 8 pages; each page is 2048 byte long, mapped onto a physical memory of 64 frames.(i) How many bits are there in the logical address and how many bits are there in the physical address?(ii) A 6284 bytes program is to be loaded in some of the available frames ={10,8,40,25,3, 15,56,18,12,35} . Show the contents of the program's page table.(iii) What is the size of the internal fragmentation?(iv) Convert the following logical addresses 2249...
Consider a logical address space of 256 pages with a 4-KB page size, mapped onto a physical memory of 64 frames. a. How many bits are required in the logical address? b. How many bits are required in the physical address?
A computer uses a byte-addressable virtual memory system with a four-entry TLB and a page table for a process P. Pages are 16 bytes in size. Main memory contains 8 frames and the page table contains 16 entries. a. How many bits are required for a virtual address? b. How many bits are required for a physical address?
The RISC-V 32-bit architecture supports virtual memory with 32-bit virtual addresses mapping to 32-bit physical addresses. The page size is 4Kbytes, and page table entries (PTEs) are 4 bytes each. Translation is performed using a 2-level page table structure. Bits 31:22 of a virtual address index the first-level page table. If the selected first-level PTE is valid, it points to a second-level page table. Bits 21:12 of the virtual address then index that second-level page table. If the selected second-level...
1) Given a virtual memory system with: virtual address 36 bits physical address 32 bits 32KB pages (15 bit page offset) Each page table entry has bits for valid, execute, read and dirty (4 bits total) and bits for a physical page number. a) How many bits in the page table? (do not answer in bytes!) Three digit accuracy is good enough. The exponent may be either a power of 2 or a power of 10. b) The virtual address...