Question

10.12) Consider a two-processor system with two MESI caches, C0 and C1. Suppose the processors execute two threads, T0 and T1, that share variable A. Outline a scenario when the MESI transition E(XWH) → I will take place, assuming memory block B(A) contains A.

Answer 1

• The MESI convention is an invalidate- based reserve intelligibility convention, and is a standout amongst the most well-know conventions which support compose back stores
• It is otherwise called the Illinois convention
• compose back stores can spare great deal on transmission capacity that is commonly squandered on a compose through reserve.
• There is dependably a grimy state present in compose back reserves which shows that the information in the store is not quite the same as that in fundamental memory.
• This convention lessens the quantity of main memory exchanges as for the MSI convention

STATES

• Modified(M):: the cache line present in the current cache and is dirty. it has been modified from the value in main memory
• Exclusive(E):: the cache line present in the current cache but it is clean. it matches main memory
• Shared(S):: it indicates cache line stored in other cache of the machine and it is clean.
• Invalid(I) :: indicates cache line is invalid

EXAMPLES: HOW MESI PROTOCOL WORKS

• cache line changes state as a function of memory access event
• Event may be either

            --> due to local processor activity

            ---> due to bus activity

• cache line has its own state affected only if address matches
• Operations can be defined informally by looking at action in local processor

              Read Hit

              Read Miss

            Write Hit

            Write Miss

• During system reset, the MESI bits for the caches c0 and c1 are set to I= Invalid
• this makes all lines empty and will force any caches read or write to miss
• At first read , lines will be streamed in to c0 and a portion of those to be streamed into C1
• Since C0 has a copy of what is in C1 and C0 is set to S and C1 is set to E
• E holds as long as no other processor's cache shares the same data
• If B has not yet made any data accesses, hence its cache lines remain I

KEY ISSUES

• Scaling of memory and directory bandwidth

       ----> can not have main memory or directory memory centalized

     ------->Need a distributed memory and directory structure

• Directory memory requirements do not scale well

      -------> Number of presence bits grows with number of PE's

    ---------> Many ways to get around this problem

• Industry standards

        ---> SCI: Scalable Coherent Interface