Simplify the circuit below to obtain the most simplified SOP implementation using any method. Dra...
Simplify the circuit below to obtain the most simplified SOP implementation using any method. Draw a timing diagram for the truth table of the circuit below. Assume each input combination lasts for 20 ns and the propagation delay from the input of the circuit to the output is a total of 10ns. See slide 61 of Chapter 2 slides for an example of an "ideal but with delay" timing diagram for the output. (12 pts) 1. 10 Find the critical path and the fastest path for the circuit above and indicate their delays. The delays are as follows: NOT 1ns, AND 3ns, OR - 3ns, NAND 2ns, NOR 2ns, XOR 4ns. Write the paths in terms of the gate numbers (e.g.: 1-5-7-10 11ns). (12 pts) 2.
Simplify the circuit below to obtain the most simplified SOP implementation using any method. Draw a timing diagram for the truth table of the circuit below. Assume each input combination lasts for 20 ns and the propagation delay from the input of the circuit to the output is a total of 10ns. See slide 61 of Chapter 2 slides for an example of an "ideal but with delay" timing diagram for the output. (12 pts) 1. 10 Find the critical path and the fastest path for the circuit above and indicate their delays. The delays are as follows: NOT 1ns, AND 3ns, OR - 3ns, NAND 2ns, NOR 2ns, XOR 4ns. Write the paths in terms of the gate numbers (e.g.: 1-5-7-10 11ns). (12 pts) 2.