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Experiment Description: Write a Verilog module for the 4256ZE Development Board that displays four different character sequen IGNORE FIRST PART. JUST DO THE PRELAB STEP 1 PART PLEASE.
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Moclule seq ); output weq [6:01 seq always begin case CDISP 2b00:begin &# 1 segニ731111011; seg 1b 110 0111, Se 001i or blooseg = ㄱb1011011 end 2b10 begin Seg- 7bz se9: ㄱ b0001110, #li Seablo01111 seq = 7 boooo 111) 射1; ses-ть 1100111) end 2

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