Question

The following is the layout of an inverter with dimensions. Assume that V_DD=2.5V, K’_n=100uA/V², V_tn=0.4V, K’_p=60uA/V², V_tp=-0.5V, t_ox=12nm, ε_ox=3.9, X_d=42nm(overlap distance under the gate), C_j=0.74fF/um², C_jsw=0.43fF/um for both NMOS and PMOS devices at zero bias.

a.) Estimate the effective input capacitance of the inverter, C_in.

b.) Estimate the effective output capacitance of the inverter, C_out. For simplicity find effective C_out at zero bias.

c.) If the output of this inverter is connected to a similar inverter, estimate the t_PHL and t_PLH. Ignore the wire parasitic capacitance.

A (input) 0.6um0.6um 0.5um 20.5um 0.25um 0.25um

Answer 1

Fuom Layout of nvedter し=o.as μ.m Groven Parameter Eox = 3,9 acitance hese , Y 42nm gren-

- Eox toメ -15 -12 12 χ to Sie Can

2(0.14) 2 0.43 R4.KX10-Ts厂10. 04X10-R t о.Cad ニ t. 4rt 0.863

here So, tne Ea Rn Kn 0.0019 &

o?,Rナ6, oo 19g-ナ293.ar 3 Rp BP fr= 144

. Re , Rp 0.00347 243.2 IS X lo