Question

6. Below is shown three-stage JFET amplifier circuit. VDD 15V loss 16 mA Vp--3V 1.1 k2 1.1 k2 (JFETS J1 - J3) J1 0.1 uF J2 0.1 μF J3 500 Ω 0.1 μF sig 1 ΜΩ 2000 2000, 1 ΜΩ 2000 1 ΜΩ 180 Ω Lu a) Find the input impedance, output impedance, and no-load voltage gain for each of the three stages. b) Find the loaded voltage gain for each of the stages. c) Find the overall voltage gain and the overall current gain for the three- stage configuration.

Answer 1

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Αν 19.24