Question

(Hazard Detection Unit problem)

The figure shows an additional element added to the CPU to deal with hazards: the hazard detection unit. This one is designed to help avoid stalls resulting from a different type of instruction. Fush detection DVEX MI EX RegistersE Data memory ,リ memory Sign Fowarding a) Name all of the instruction(s) listed anywhere on the MIPS data reference sheet that the hazard detection unit assist in resolving. (Include pseudocode instructions if applicable. Give only the mnemonic.) What instruction does the branch hazard unit insert into your code to create a stall? Does the branch prediction unit always have to insert a stall? Yes or No? b) c)

Answer 1

THE HAZARD DETECTION UNIT

(a)

• The hazard detection unit's inputs as follows

IF/ID .Register Rs and IF/ID .Register Rt,the source register for the current instruction

            ID/EX.MemRead and ID/EX.RegisterRt, to determine if previous instruction is LW and if so, which register it will write to

• the detection unit generates three outputs

      -->    two new control signals PCWrite and IF/ID write------> determines whether the pipeline stalls or continues

----> A mux select for a new multiplexer , which forces control signals for the current EX and future MEM/WB stages to 0 in case of a stall

• the hardware does not depend on the compiler to detect and eliminate data hazards
• A smart compiler will help in order to achieve better performance
• consider this sequence

        sub2,1,3

        and12,2,5

        or 13,6,2

        add 14,2,2

        sw 15,100(2)

• resolve hazards with forwarding
• Pass register numbers along pipeline

          e.g ID/EX.RegisterRs = register number for Rs sitting in ID/EX pipeline register

• ALU operand register numbers in EX stage are given by

          ID/EX.RegisterRs, ID/EX.Register Rt

• Data hazards when

          EX/MEM.RegisterRd = ID/EX.RegisterRs

          EX/MEM.RegisterRd = ID/EX.RegisterRt

          MEM/WB.RegisterRd = ID/EX.RegisterRs

          MEM/WB.RegisterRd = ID/EX.RegisterRt

• But only if forwarding instruction will write to a register

        EX/MEM.RegWrite, MEM/WB.RegWrite,

• And only if Rd for that instruction is not zero

            EX/MEM.RegisterRd $\neq$ 0

           MEM/WB.RegisterRd $\neq$ 0

• EX hazard

        ----> if (EX/MEM.Reg Write and ( EX/MEM.RegisterRd $\neq$ 0)

              and (Ex/MEM.registerRd =ID/EX .RegisterRs))

             ForwardA= 10

    ------> if (EX/MEM.Reg Write and ( EX/MEM.RegisterRd $\neq$ 0)

              and (Ex/MEM.registerRd =ID/EX .RegisterRt))

             ForwardB= 10

• MEM hazard

   

----> if (MEM/WB.RegWrite and ( MEM/WB.RegisterRd $\neq$ 0)

              and (MEM/WB.registerRd =ID/EX .RegisterRs))

             ForwardA= 01

    ------> if (MEM/WB.RegWrite and ( MEM/WB.RegisterRd $\neq$ 0)

              and (MEM/WB.registerRd =ID/EX .RegisterRt))

             ForwardB= 01

• IF HAZARD IS DETECTED , stall and insert bubble

(b)

• most of the work for a branch computation is done in the EX stage
• the branch target address is computed
• the branch decision cannot be made until the end of the EX stage. but we need to know which instruction to fetch next, in order to keep the pipeline running. this leads to control hazard

DATE PAGE clack cyle clock Cyel 3 Im I C A Onc 나 Re om

• lw 2,20(1)

          and become nop

         and 4,2,5

        or 8,2,6

        add 9,4,2

• bulbble is stall
• here we just stall until cycle 4, after we do make the branch decision.

(c) NO

another approach is to guess whether or not the branch is taken. if we correct , then there is no problem and the pipeline keeps going at full speed