Question

1 bias V. out 2 2:1 mirror 6:52 PMw Variahle 2:1 mirror S Transistor PMOS Transistor Variable NMO 1 00 0.5 0.10 35 0.5 0.20 VT (V) A (1M) L (um) Vdd is 3V The bias current is 40μΑ the bias voltage at the rot. Vin-is2.8V, and thie voltage ut port a is O.7V. The load capacitance (CL) is Sp The NMOS current mirror is 2:1 NOTE: All 3 devices are NMOS above Include proper units for full credit and show your work 6:52 PM (v) What are the widths of devices 1 & 27 (4pt (v) What is the width of device 37 (2pes) (vi) Draw.the amall.sianal model What is the small signal gain (voVin) in terms of the transconductance (0m1) and the output conductance (Go1 &92) 1apts) No numbers needed (vil) What are the values of 9m1. 9o1. and Go2? (pts) (vill) What is the approximate numeric value of the small signal gain if you assume 9m1 901 and Go2? (2pts (ix) What is the value of the input resistance (Rin)? (2pts) (x) What is the value of the output resistance (Rout)? (2pts -jz. E. TTTArial " T, 3(12ㅴ ck Sove and Submit to sove and submit. Click Sove All Answers to sove all answers Question 5 6:52 PM

Answer 1

From the table given,

biot m-M

2 o 2

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