Question

This is the Prescott iteration of the Pentium 4 CPU. Can someone explain to me in detail how this diagram actually works?

Instruction TLBI Prefetcher Instruction Decoder ExecutionTrace Cache Front-End BTE te Microcode ROM Trace Cache BTB Bus Interface Unit (12K μ0ps) μ0p Queue 2K Entries nte Quad Pumped 6.4 GB/s Integer Register FileB ss Network P RegisterBypass L2 Cache FP MMX SSE SSE2 ALU AGU AGU 2x ALU 2x ALU (1M Byte FP Move 8-way) Complex Instr Load Store Simple Instr Simple Instr Address Address 108GB/s 256 bits L1 Data Cache (16Kbyte 8-way)

Answer 1

BTB and ITLB:

• Determines next instructions to be fetched from L2 cache in case of a TC miss.

The Instruction Decoder:

• Takes bytes delivered from the L2 cache and decodes them into uops.

The Trace Cache:

• Caches uops from the instruction decoder.
• Used as L1 instruction cycle.
• Delivers 3 uops/clock.
• The micro -code ROM has the micro code sequences.

Uop Queue:

• Hold uops from TC ,ucode ROM,or decode logic.
• Decouples the FE from the OOO Execution Engine.

The Renamer:

• Maps arch registers onto 128 deep physical register file.

The Allocator:

• Assigns all the necessary hardware buffers in the machine for this Uop to execute.

The Schedulers:

• Determines when a Uop is ready to execute.

Execution Units:

• up to 4 integer arithematic operations per clock cycle.
• 1 Floating point operation per clock cycle.
• A memory load and store operation (upto 128 bit) each clock cycle.