Question

Clock Divider ​​​​​​

156 Common Counter Use: Clock Divider . Freq. of a physical oscillator is fixed If we have a 512 MHz oscillator, butnt8-bit up-counter tc want a 2 MHz clock OSC 8 512 MHz Need to divide the oscillator freq. by 256 Design using an 8-bit binary up-counter, and use tc output as pulse Counts from 0 to 255 (256 counts), so tc (unused) 2 MHz pulses every 256 cycles . Issue: the duty cycle of this clock is not 50% cnt 8-bit up-counter Oscillator Solution: use a D flip-flop. The output pulse Clock (t) from the counter generates a rising edge (512MHz) for triggering the D flip-flop to toggle tc Fast Clock 254 Counter Value 253 0 255 System Clock (2MHz) Slow Clock Slow Clock (50% Duty Cycle)

can i get some simple explanation ( what I'm suppose to understand from this)

my lecturer explains it but I honestly don't understand what statements he's trying to make

my understanding :

there's a frequency input of 512 Mhz, since we know 8 bit counter can count up to 256, it will do it once before it rolls overload (???)

can someone please clarify and point out the important facts that i should be undertanding

please and thank you

Answer 1

For the frequency divide logic 8 bit counter means we have 8 possible states sta that we need 3 Flip flop. If the frequency is100Hz then output of frequency will be 33.33Hz.

2^N counter means N=number of Flip flop

2^N = number of possible states.

Any frequency you need from given frequency, we need to apply frequency divider rule, number of Flip flop required , number of states output we make it high.