Question

[6 marks Consider the following MIPS code. Determine which registers are being read and which register will be written at the fifth cycle? 5) dd $t4, $t5 St6 dd $t7, $t8, $t9

Answer 1

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As we can see from the above pipelined execution diagram a 5 clock cycles we have two instruction which are performing read and write on register

• Instruction 1 add $s1 $s2 $s3
• Instruction 4 add $t4 $t5 $t6

so write is performed by instruction 1 and read by instruction 4 at 5th cycle

so register written will be $s1

and read will be $t5 $t6