Question

10. You are using a 16-bit timer, time are using PBCLK, an internal c r1, which has pre ock, hihh has pre-scale options of 1:1, 1.3, 1.64,and 1.256. You configured to run at 10MHz. PRESET EXT CLK COMPARATOR INT CLK Is it possible to set the preset register to a value that corresponds to a time interval of 1.70 seconds, so that the timer can count from 0 to the value and generate an interrupt? You must justify your answer. A yes/no answer will get no points 01 2 (a

Answer 1

Answer :- No.

Here clock frequency is 10 MHz, if we use highest pre-scaling value i.e. 256, the clock to timer is 39062.5 Hz. Hence the number of clock pulse required to make delay of 1.7 second is-

n = 1.7*39062.5 = 66406.25

Since value of n is greater than maximum timer count 65536(since 16-bit timer), thus 1.7 s delay can not be generated.