Question

This is the 2-bit multiplier truth table.

z000 0010-1000-00 101 Y000 0001101010110 X0000000000110010 W-0000000000000001 D0-01-01 01 01010101 C00-10011001-10011 ut B0000-11-100001111 A0000000011111111 012307 23012-30123 000011_1122223333

How can I design a 2-bit multiplier using just NAND gates from SOP format?(use the  De Morgan’s Law)

Answer 1

อ000 oO 0 O ol o o o to lo ol οιοσ l o l o I I L 13 1 10 0 Iy so

·꺼 Ag C X= Acht ABC AR 0心 A BC, 이 → BCD io ABD ACD

p fora BD NAND 8 C. BD

Bc C. BCAD A D