Question

Arrays A and B contain 1 K (1024) elements each. Each element is 4 bytes. The first element of A (A[O]) is stored at physical address 0x0000 4000. The first element of B (B[O]) is stored at physical address 0x0001 8000. A physical address is 32 bits. Assume that only arrays A and B will be cached in the following fragment of code (i.e., the index i will be in a register): for i 1023; i 0; i-) Alil-i The cache is a 4 KB direct-mapped cache with line size 16 bytes. The write policy is writeback. Initially, all entries in the cache are marked as invalid. (a) How many cache lines are there in the cache? (b) What will be the cache contents at the end of the program fragment(i.e., when all 1024 iterations of the loop have completed)?

Answer 1

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