1. [20 Pts] You are given the data-path below. Note that there are three registers. Two of these have a load control input, while the other loads a new value on every clock cycle. There are two t...
1. [20 Pts] You are given the data-path below. Note that there are three registers. Two of these have a load control input, while the other loads a new value on every clock cycle. There are two tri-state drivers that connect the outputs of registers A and Bto a common bus. Finally, there is an ALU that can perform two operations: .Pass Y add X and Y X is always the output of register C, while Y is the value on the bus oadA Bus |Pass/Add' egA RegC ALU LoadB egB BtoBus a) [10 Pts] Show the register-transfer operations needed to implement an instruction that swaps the contents of the A and B registers (SWAPA, B). Make sure to clearly indicate how many clock cycles will be needed to implement the instruction and the value of each control signal in each state (use the provided table). Cyde Operation AtoBus BtoBu ALU LoadA LoadB
1. [20 Pts] You are given the data-path below. Note that there are three registers. Two of these have a load control input, while the other loads a new value on every clock cycle. There are two tri-state drivers that connect the outputs of registers A and Bto a common bus. Finally, there is an ALU that can perform two operations: .Pass Y add X and Y X is always the output of register C, while Y is the value on the bus oadA Bus |Pass/Add' egA RegC ALU LoadB egB BtoBus a) [10 Pts] Show the register-transfer operations needed to implement an instruction that swaps the contents of the A and B registers (SWAPA, B). Make sure to clearly indicate how many clock cycles will be needed to implement the instruction and the value of each control signal in each state (use the provided table). Cyde Operation AtoBus BtoBu ALU LoadA LoadB