Question

ofe 4X2 priority encoder in VHDL. The operation of priority is such Given the imp that iT two or more inputs are equal to I at the same time the input having the highest priority takes precedence according to the following table. Write the Testbench to test 4 different cases of nputs inputs Outpab A2 АЗ Ai A0

Answer 1

Answer 1)

VHDL Code for the priorty encoder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity priority_encoder is
port(
A3, A2, A1, A0 : in std_logic;
F1, F0, void : out std_logic
);
end priority_encoder;

architecture pr_en of priority_encoder is
begin

process(A3, A2, A1, A0)
begin
if (A3 = '1') then
F1 <= '1'; F0 <= '1'; void <= '1';
elsif (A2 = '1') then
F1 <= '1'; F0 <= '0'; void <= '1';
elsif (A1 = '1') then
F1 <= '0'; F0 <= '1'; void <= '1';
elsif(A0 = '1') then
F1 <= '0'; F0 <= '0'; void <= '1';
else
F1 <= '0'; F0 <= '0'; void <= '0';
end if;
end process;

end pr_en;

Testbench for the above priority encoder

library ieee;
use ieee.std_logic_1164.all;

entity priority_encoder_tb is
end priority_encoder_tb;

architecture behavior of priority_encoder_tb is

-- component declaration for the unit under test (uut)

component priority_encoder
port(
A3 : in std_logic;
A2 : in std_logic;
A1 : in std_logic;
A0 : in std_logic;
F1 : out std_logic;
F0 : out std_logic;
void : out std_logic
);
end component;
  

--Inputs
signal A3 : std_logic := '0';
signal A2 : std_logic := '0';
signal A1 : std_logic := '0';
signal A0 : std_logic := '0';

    --Outputs
signal F1 : std_logic;
signal F0 : std_logic;
signal void : std_logic;
  
BEGIN
   
uut: priority_encoder port map (
A3 => A3,
A2 => A2,
A1 => A1,
A0 => A0,
F1 => F1,
F0 => F0,
void => void
);

stim_proc: process
begin      
A3 <= '0'; A2 <= '0'; A1 <= '0'; A0 <= '0'; wait for 10 ns;
A3 <= '0'; A2 <= '0'; A1 <= '0'; A0 <= '1'; wait for 10 ns;
A3 <= '0'; A2 <= '0'; A1 <= '1'; A0 <= '0'; wait for 10 ns;
A3 <= '0'; A2 <= '0'; A1 <= '1'; A0 <= '1'; wait for 10 ns;
A3 <= '0'; A2 <= '1'; A1 <= '0'; A0 <= '0'; wait for 10 ns;
A3 <= '0'; A2 <= '1'; A1 <= '0'; A0 <= '1'; wait for 10 ns;
A3 <= '0'; A2 <= '1'; A1 <= '1'; A0 <= '0'; wait for 10 ns;
A3 <= '0'; A2 <= '1'; A1 <= '1'; A0 <= '1'; wait for 10 ns;
A3 <= '1'; A2 <= '0'; A1 <= '0'; A0 <= '0'; wait for 10 ns;
A3 <= '1'; A2 <= '0'; A1 <= '0'; A0 <= '1'; wait for 10 ns;
A3 <= '1'; A2 <= '0'; A1 <= '1'; A0 <= '0'; wait for 10 ns;
A3 <= '1'; A2 <= '0'; A1 <= '1'; A0 <= '1'; wait for 10 ns;
A3 <= '1'; A2 <= '1'; A1 <= '0'; A0 <= '0'; wait for 10 ns;
A3 <= '1'; A2 <= '1'; A1 <= '0'; A0 <= '1'; wait for 10 ns;
A3 <= '1'; A2 <= '1'; A1 <= '1'; A0 <= '0'; wait for 10 ns;
A3 <= '1'; A2 <= '1'; A1 <= '1'; A0 <= '1'; wait for 10 ns;
wait;
end process;

end;

Waveform

200 ns 180 ns 160 ns 140 ns 120 ns 100 ns 60 ns 20 ns o ns Value Name