Question

5 Exercises Now that everything is working you can try the following exercises. To complete them you will need to refer to the documentation in Appendix A- The MiteASM Assembler and Appendix B - The MiteFPGA Processor. Write an assembly language program for an over counter for a cricket umpire. This should display a count on the 7-segment display. The count should increase by 1 when button 0 is 1. pressed. It should reset to 0 when button 1 is pressed. If the count is 6 or greater, LED O should turn on to indicate the end of the over. The assembler supports the instructions jal, jr, sll and srl but these are not yet 2. implemented in the processor. Pick one of these instructions and modify the processor SystemVerilog HDL so that the instruction is executed correctly. Write and execute a smal assembly language program to test the instruction Appendix A - The MiteASM Assembler The MiteASM assembler: egenerates instruction memory beginning at address 0x00000000. Is case sensitive for labels but assumes keywords use consistent case (i.e. use jal, or JAL but not JaL) supports instructions preceded by a label with a colon e.g.main: addi $to, s0, 0x0 uses # to indicate comments. Everything on a line following a # is ignored. * supports literal integers in hex format preceded by 0x e.g. 0x40 and decimal literals e.g 64. Negative hex (e.g. -0x40) and decimal (e.g. -64) can also be used. can use labels in place of literals e .g. j main assembles the instructions jal, jr, sll and srl although these are not executed by the processor as it is distributed. (You can always add them!) is distributed as Java source code so you can add support for other MIPS instructions. Opcode Funct Name Type Description MiteFPGA Supports 6'h00 6h00 sll R shift left logical [rd rtshamt sll Srd, Srt, shamt srl Srd, Srt, shamt No No 6'h20 add R add Srd, Srs, Srt Yes 6'h24 and R and Srd, Srs, Srt or Srd, Srs, 0 slt Srd, Srs, $rt 6'h25 or 6'h2A slt R set less than [rs[rt]? [rd] 1: [rd] PC JTA Sra-PC+4, PCsJTA JTA jal JTA beq Srs, Srt, BTA addi $rt, Srs, Signlmm Yes 6'h03 jal jump and link branch if equal (Irs][rt) PC BTA add immediate [rt] [rs] + Signimm Yes 6'h08 addi I Address [rt sw Srt, Signimm(Srs) 6'h2B Yes store word SW Table 1: instruction Set Notation Meaning [regl contents of register number reg imm 16-bit immediate field of I-type instructions addr:26-bit address field of J-type instructions Signlmm sign extended immediate 16imm [15)H, imm Address rsSignlmm contents of memory location Address BTA branch target address PC 4 Signimm

Answer 1

Electic field Given Ahat Lacatian P C1,,) with respect to ovigin o, 0.0) 2 R 6 1.ar +1.A4 + 2aZ aR = -R一ー Ie 3. 3