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Suppose we could take the system of (Figure 1) and divide it into an arbitrary number of pipeline stages k, each having a delay of 300/k, and with each pipeline register having a delay of 20 ps.
Figure:
300 ps 20 ps Combinational logic Delay 320 ps Throughput 3.12 GIPS Clock (a) Hardware: Unpipelined I1 12 I3 Time (b) Pipeline diagram
Part A What would be the latency of the system? Express your answer in terms of k. vec Latency
Part B What would be the throughput of the system? Express your answer in terms of k. vec Throughput GIPS
Part c What would be the ultimate limit on the throughput? Express your answer as in integer. vec GIPS



Part B What would be the throughput of the system? Express your answer in terms of k. vec Throughput GIPS
Part c What would be the ultimate limit on the throughput? Express your answer as in integer. vec GIPS
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