Question

Problem 7: Synchronous System Timing/Definition Memory Combinational Logic (F/Fs) tfipd 3 ns min and 15 ns max tsetup 5 ns min thold=2 ns min teomb 2 ns min and 20 ns max 1. What are the Setup and Hold Time Margins if we use a 10 MHz Clock? 2. Define briefly the synchronous circuits (FSM) Mealy and Moore Machines

Answer 1

2.

Setup Time Sep ime Margin Data Reauiked im Data ariml time eomaLrnin) - Eselsaf Atgpd.(mos) št tepmb (man)] (loo t2-5)-( 15 t 20) (97-35) na Hold tmo Margins مع سمـ Data atkival tins-Dat Hold m Mngin ime (Effpå (rmin) + eeml (mia) - (teamlr (ma) Łm l3)-ot ) 5- a217 n

Moore Machine -

(a.) Output depends only on present state.

(b.) If the input changes output does not changes

(c.) More number of states are required.

(d.) There is more hardware requirement and they react slower to inputs

(e.) Output is placed on states.

transition logic output logic output state memory input S S G T R lelock reset

Mealey Machine -

(a.) Output depends on present state as well as present input.

(b.) If the input changes output also changes

(c.) Less number of states are required.

(d.) Output is placed on transitions.

(e.) Output generation is asynchronous.

(f.) They are faster.

Output Logic Outputs Inputs Next State State Logic Register