1. Consider the following java code. int x 5 X++ Give equivalent MIPS ISA. Assume compiler...
1. Consider the following java code snippet. x = 5; X++; Give equivalent MIPS Assembly. Assume compiler will keep x in $50 ($16). 2. What will be in $8 after executing the following statements? addi $8, $0,5 add $8, $8, $8
3. What will be in $8 after execution? addi $8, $0,5 sil_$8, $8,2 // shifting $8 left twice (logical shift- assume no sign) 4. What will be in $8 after execution? Assume $9 contains a valid RAM address. .data A: 5 10 15 .text Main: la $9, A addi $10, $0,5 sw $10, 8($9) addi $9, $9,8 lw_$8, 0($9)
4. What will be in $8 after execution? Assume $9 contains a valid RAM address. .data A: 5 10 15 .text Main: la $9, A addi $10, $0, 5 sw $10, 8($9) addi $9, $9, 8 lw $8, 0($9)
4. What will be in $8 after execution? Assume $9 contains a valid RAM address. .data A: 5 10 15 .text Main: la $9, A addi $10, $0,5 sw $10, 8($9) addi $9, $9,8 w_$8,0($9)
Question 3 (10 points) Convert the following MIPS assembly code into machine language. Write the instruction in hexadecimal. The opcode for sw 43 (101011). sw St1, -4(St3) Question 4 (10 points) Consider the following MIPS assembly code: addi $s3, $0, 5 addi $s1, S0, 3 addi Ss1, $s1, 2 beq Ss3, Ssl, target addi Ss1, Ss1, 1 target: add Ss3, Ss1, Ssl a. After running the code, what is the value of Ss3? b. If the memory address of the...
Topics 1. MIPS instruction set architecture (ISA). 2. Performance. 3. MIPS datapath and control. Exercise 1 Consider the memory and register contents shown below. Registers Ox0100 FFF8 13 ($t 5) 14 ($t6) 0x0100 FFFC 0x0101 0000 Memory 0x0000 0000 0x0001 1100 0x0A00 со00 0x1234 4321 OxBAOO OOBB 15 OXAAAA 0000 0x1111 1010 0x7FFF FFFD 0x0100 FFFO 0x0101 0008 (St7) Ox0101 0004 16 ($80) 0x0101 0008 17 ($sl) Show what changes and give the new values in hexadecimal after the following...
Please comment the MIPS code to help me understand. Here is what the code accomplishes. Here is the code, partially commented. .data Matrix: .word 41,45,5, 34,8, 15,16,23,44,48,12,32,18,47,22,8,22 .word 46,40,42,33,13,38,27,6, 29,25,18,40,47,22,26,14,3 .word 7, 48,35,9, 43,38,9, 49,28,25,42,5, 44,10,5, 38,14 .word 46,33,16,6, 13,20,31,1, 8, 17,1, 47,28,46,14,28,7 .word 32,2, 48,25,41,29,14,39,43,46,3, 39,32,49,41,28,46 .word 5, 43,2, 48,13,4, 33,41,32,19,9, 25,30,22,2, 9, 40 .word 14,47,22,18,47,3, 35,44,18,6, 33,22,11,6, 47,50,4 .word 28,34,20,30,18,27,38,5, 26,40,37,23,16,13,37,8,7 .word 48,38,39,12,10,39,23,20,21,20,33,16,24,21,25,3,46 .word 49,38,40,38,13,47,5, 13,4, 13,23,26,12,30,29,29, 3 .word 8, 20,10,13,31,7, 12,41,12,21,28,26,43,14,35,10,19 .word 49,33,25,26,24,29,46,22,7, 5, 15,41,10,31,19,41,27 .word 48,9,...
2. Q2 [25 points) Consider the MIPS code given in the following. main: addi Ssp, Ssp, -4 addi Sa0, $0, 2 sw $a0, 4(Ss1) addi Sal, $0, 3 sw Sal, 8(Ss1) jal dofsum sw SvO, 16(8s1) lw Sra, O(Ssp) addi Ssp, Ssp, 4 jr Sra dofsum: jal sum jr Sra sum: add SvO, Sa0, Sal jr Sra Draw the snapshot of the stack before, during, and after dofsum) function call. As- sume SSP, 0x45fff00 before dofsum() function call.
We’re executing the following instruction sequences on a 5-stage MIPS pipeline. Add R8, R9, R10 Lw R14, 0x0020(R12) Or R16, R9, R10 Sw R12, 0x0020(R10) Addi R20, R21, 5 (1) At cycle 5, what action (add, sub, and, or) is ALU performing? (2) At cycle 5, what is the action (read, write, no action) of DM? (3) At cycle 5, which registers are being read out? (4) What is the speedup comparing with the unpipelined execution of the same instruction...
We’re executing the following instruction sequences on a 5-stage MIPS pipeline. Add R8, R9, R10 Lw R14, 0x0020(R12) Or R16, R9, R10 Sw R12, 0x0020(R10) Addi R20, R21, 5 (1) At cycle 5, what action (add, sub, and, or) is ALU performing? (2) At cycle 5, what is the action (read, write, no action) of DM? (3) At cycle 5, which registers are being read out? (4) What is the speedup comparing with the unpipelined execution of the same instruction...