Question

Design a 3-bit synchronous counter that counts the sequence 7, 4, 2, 1, 6, 5, 7, ect. Use "don't-cares" for the "next states" of the unwanted states. Use a D flip flopfor the most significant bit, a T flip flop for the middle bit, and a JK flip flop for the least significant bit. Use SOP.

Answer 1

First of all we draw the excitation table for the different flip flops
Q_n Q_n+1 D T J K
0 0 0 0 0 X
0 1 1 1 1 X
1 0 0 1 X 1
1 1 1 0 X 0

then we draw the state transition table for following the sequence 7,4,2,1,6,5,7.

let the MSB bit be A then 2^nd bit be B and the LSB bit be C . then the table will be

A_n B_nC_n A_n+1B_n+1 C_n+1DT JK
1 11 1 001 1X 1
1 0 00 100 10 X
0 1 00 01 011 X
0 0 11 101 1X 1
1 1 01 0 111 1 X
1 0 11 111 1X 0

now we make D , T , J , K as a function of A_n , B_n , C_n respectively by reducing the functions in a karnaugh map.

FOR D(A_n,B_n,C_n)
00 01 1110 A_n B_n

	1	1
		1	1

0 C_n _
1D= C_nB_n+C_nA_n




FOR T(A_n,B_n,C_n)
00 01 1110 A_n B_n

1	1	1	1
1	1	1	1

0 C_n
1T=1 (logic 1)

FOR J(A_n,B_n,C_n)
00 01 1110 A_n B_n

X	1	1
X	X	X	X

0 C_n
1j= B_n

FOR k(A_n,B_n,C_n)
00 01 1110 A_n B_n

X	X	X	X
1	X	1	0

0 C_n _
1K=A_n +B_n

HENCE THIS IS THE DESIGN FOR THE REQUIRED COUNTER .

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