Question

Example 4.2 For all three cases, the example includes the following elements: The cache can hold 64 Kbytes. Data are transferred between main memory and the cache in blocks of 4 bytes each. This means that the cache is organized as 16K = 214 lines of 4 bytes each. The main memory consists of 16 Mbytes, with each byte directly addressable by a 24-bit address (24 = 16M). Thus, for mapping purposes, we can consider main memory to consist of 4M blocks of 4 bytes each 1. (12 points) Assume the cache and memory are the same as shown in Example 4.2 a. For the hexadecimal main memory addresses F6125Chex, When it is loaded to cache memory using direct mapping, where will it be stored? Show the following information in hexadecimal format: Tag and Line number b. If the next instruction is the content stored at 160004hex in main memory and in cache memory, line number 0001hex has a tag 00hex- Will we have a cache hit event or cache miss, why? (hint: check the line number and tag of 160004, if matches with the cache line, then cache hit; Otherwise, cache miss

Answer 1

MON TUE WED THU FRI SAT SUN ロロロ cache siye Ck byfes Blork e4 bytes Numberr odBlocks in cache 14 16K = 4 cam ge16mB Numberr af Ublocks in ain m Main m emohy 4mB-2 16 mB Llocks 4 bytes require 2 bits 2 6locles iuaeauire lu bits 24-C2+14) will iu be 8 bits 17 Tag I4 2 BLOcles BYTE TAG

Date a) Addues guis F6125Cher Biaany farrat 1/ ) I100 0001 0010 00 ST 2 TAG inett At line numbe o491 o001001o0101 be atared cache this Block ls

Date MON TUE wED TUU FR 6) Nout wntucton 160004 termat Binyg oll o O o00 Oo00 0l00 16hnC TAG- Line numbe n cache at linu o00l at corhe tag o0olh the data io 0Onent 9t means line oth lock o man mem deasty it will o a rarhe misc tegio aaŁsame the