Question

Please use system verilog:

03. Using FSM technique, write an HDL code for a traffic light controller with 3-bit active-high outputs (Red, Amber, and Green lights, respectively) for a 4-way intersection (North, East, South, West) that cycles through the states (ie. SO S1 S2 S3 SO etc.) for each trigger according to the scheme shown in the table below (default state So): States North East South West 34 North 37, SO100 East 001 100 Traffic Light Controller 001 3 South S1100010100010 3', West S2 001 100 001 100 S3010 100 010100 trigger (e.g. 100 represents Red light is on, while Amber and Green lights are off.)

Answer 1

Solution:

--VHDL Code

library ieee;
use ieee.std_logic_1164.all;

entity controller is
port ( trigger : in std_logic;
north : out std_logic_vector(2 down to 0);
east : out std_logic_vector(2 down to 0);
south : out std_logic_vector(2 down to 0);
west : out std_logic_vector(2 down to 0)
);
end controller;

architecture arch of controller is

type state is (S0, S1, S2, S3);
signal present_state, next_state : state;

begin

process (present_state)

begin

case present_state is

when S0=> north <= "100"; east <= "001"; south <= "100"; west <= "001"; next_state <= S1;
when S1=> north <= "100"; east <= "010"; south <= "100"; west <= "010"; next_state <= S2;
when S2=> north <= "001"; east <= "100"; south <= "001"; west <= "100"; next_state <= S3;
when S3=> north <= "010"; east <= "100"; south <= "010"; west <= "100"; next_state <= S0;
when others => null;
end case;

end process;

process (trigger)

begin

if rising_edge (trigger) then
present_state <= next_state;
end if;

end process;

end arch;

--Simulated on MultiSim

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