Question

Hello, I was wondering if anyone could answer a question for me. The question is: I wanted to know what factors effect the power consumption of a CMOS logic gate? Specifically how the input voltage levels, power supply voltage, and clock frequency affects the CMOS logic gate.

Answer 1

The static power consumption, that is power consumption when all inputs are at some logic level and when the circuit is not charging is very low as it because of leakage current. The average dynamic power consumption due to switching depends on power supply voltage V _DD, load capacitance C_L, clock frequency f as given by the formula Pd=C_LV_DD²f

The short circuit power dissipation depends on supply voltage V_DD, threshold voltage V_t, rise time=fall time=t_if and period t_p as follows:

Psc=(beta/2)(V_DD-2V_t)³(t_if/t_p)