Question

Equations may require: Po fCV.2 1. Describe the read operation and write operation for a 6T-SRAM. Also, describe the purpose of Sense-amplifier, Driver and Precharge circuits for the memory made of 6T-RAM. If we have to design 4-GByte SRAM, how many transistor will be required only for the memory? 2. What the advantages and disadvantages bet NOR-based, NAND and T-column decoder? 3. Describe the read and write operation in Flash memory made of floating gate transistor. Draw the figure of channel when "1" and "O" is stored in the cell made of floating gate transistor 4. A particular 1-M-bit-square memory array has peripheral circuits reorganized to allow for the readout 16-bit word. How many address bits will the new design need a) How many word lines must be supplied by the row decoder? b) How many sense amplifiers/drivers would a straight forward implementation require? c) If the chip power dissipation 500 mW with a 5-V supply for continuous operation with 20 ns cycle time, and all the power loss is dynamic, estimate total capacitance of all logic activated in any one cycle. d) We assume that 90% of this power loss occurs in array access, and that the major capacitance contributor will be line itself, calculate the capacitance per bit line and per this design. (Remember that 16 bit li selected simultaneously.) If closer manufacturing control allows the memory array to operate at 3V, how much large memory array can be designed in the same technology about the same power level?