Question

please show steps will be greatly appreciated and will rate thanks in advanced

Consider the logie equation Y-NOT. (A B IC+D+E a. Sketch the circuit using Complementary CMOS design<10%) h. Sketch lhe cireuit uang Pseud-NMOS realizalin of the lyric equation. (10%) e. Sketch the circuit ning Dynamic logic (10% }

Answer 1

Y = NOT { A + B (C + D + E) = A + B (C + D + E) @ PMOS y = A + B (C + D + E) y = A . B (C + D + E) y = A . { B + C D E } y = A. { B + C D E } = A + B (C + D + E) y = A + B (C + D + E) NMOS In pseudo NMOS sing PMOS rightarrow connected to ground gate Input if phi = 0 , PMOS rightarrow charged y to v_dd phi = 1: NMOs evaluates Logic , depending on inputs.